Using Verilog Simulation Libraries for ATPG

Authors:
Peter Wohl;John Waicukauski
Affiliations:
-;-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

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Abstract

Significant engineering effort is invested into coding librariesfor automatic test pattern generation (ATPG) and verifyingtheir equivalence with corresponding "golden"simulation libraries.These tasks are greatly simplified byusing the methodology and the ATPG described in thispaper.Simulation libraries are read-in with little or no recoding.Various structural and some behavioral Verilogconstructs are automatically converted into efficient gate-levelmodels for ATPG.