Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
IEEE Transactions on Computers
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Using Verilog Simulation Libraries for ATPG
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Modeling Custom Digital Circuits for Test
Journal of Electronic Testing: Theory and Applications
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Most library development effort is invested in coding andverifying custom or special function cells that cannot be easilyrepresented by traditional gates such as AND, OR, andare naturally encoded as tables. The library readerdescribed in this paper reads in existing simulation librariesand converts tables into efficient gate-level models for useby test-generation and other tools, thus automating the mostengineering-intensive task of library development.