Operation and modeling of the MOS transistor
Operation and modeling of the MOS transistor
Extraction of Schematic Array Models for Memory Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Solution for Hardware Emulation of Non Volatile Memory Macrocells
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Algebraic model for the behaviour of a D-flip-flops-based memory component
MAMECTIS'10 Proceedings of the 12th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems
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In this paper, three EEPROM memory cell models are presented. The first model is a compact model based on Mos Model 11 (MM11) and fully validated on silicon. From this first model we propose two alternative models (level 1 & level 2). These last models allow a reduction of simulation time and memory space overheads, with respect of accuracy, compared to the original compact model. The technique used to build the level 1 and level 2 models is based on the complexity reduction of the original EEPROM model. We also present simulation time results using the different models within memory arrays.