RTL emulation: the next leap in system verification
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A reconfigurable logic machine for fast event-driven simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Device and memory array models for flash EEPROM technology
WSEAS Transactions on Circuits and Systems
Device and memory array models for flash EEPROM technology
WSEAS Transactions on Circuits and Systems
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More and more the system verification makes use of hardware emulation techniques that allow a speed up in simulation performance up to thousand times. Typically, a design is composed by several parts, most of them are available as RTL code, other, mainly memories, only like behavioral models. In this scenario coemulation is necessary to verify the heterogeneous system descriptions, but this way most of the advantage of hardware emulation is lost. This paper presents a solution for modeling the analog array of a non volatile memory based on a VHDL synthesizable description. The presented approach relies on static RAMs and ROMs which models for emulation are assumed to be available. The adoption of a synthesizable model for the analog block makes possible the mapping of the entire design on the emulator thus exploiting its performance at full speed for efficient simulation sessions.