Communication and Concurrency
Digital Design
Device and memory array models for flash EEPROM technology
WSEAS Transactions on Circuits and Systems
Counter register: algebraic model and applications
WSEAS Transactions on Computers
Algebraic model for the intercommunicating hardware components behaviour
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
Toward in vivo digital synchronous sequential circuits
WSEAS Transactions on Circuits and Systems
Algebraic model for the CPU logic unit behaviour
Proceedings of the 15th WSEAS international conference on Computers
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Before the circuits manufacturing and proceeding to the expensive component assembly, it is efficient to have a mathematical model appropriate for removing all the possible design errors. We are interested in our work to make use of these ideas for the specific case of a computer system. In this paper we apply a mathematical model and appropriate computational techniques for modelling and verifying the behaviour of a given memory component of computer systems. Specific process algebra is used here for studying the concurrent communicating processes involved in the computer memory component behaviour. Our original contributions here refer two directions, namely to define the appropriate agents for modelling the internal memory circuits behaviour and to formally prove the corresponding bisimilarities between these agents.