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ACM SIGCSE Bulletin
Recursive array layouts and fast parallel matrix multiplication
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IEEE Transactions on Parallel and Distributed Systems
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation
Journal of Systems Architecture: the EUROMICRO Journal
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Localized asynchronous packet scheduling for buffered crossbar switches
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Probabilistic system-on-a-chip architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Implementation of supervisory control using extended finite-state machines
International Journal of Systems Science
Constraint Minimization for Efficient Modeling of Gene Regulatory Network
PRIB '08 Proceedings of the Third IAPR International Conference on Pattern Recognition in Bioinformatics
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
Design of A 100MHz 64-point FFT processor in 0.35µm standard CMOS technology
MINO'09 Proceedings of the 8th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
ICCOM'08 Proceedings of the 12th WSEAS international conference on Communications
A fast computerized method for automatic simplification of boolean functions
ISTASC'09 Proceedings of the 9th WSEAS International Conference on Systems Theory and Scientific Computation
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
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EHAC'10 Proceedings of the 9th WSEAS international conference on Electronics, hardware, wireless and optical communications
A new technique for realization of Boolean functions
AIKED'10 Proceedings of the 9th WSEAS international conference on Artificial intelligence, knowledge engineering and data bases
AES and confidentiality from the inside out
ICACT'10 Proceedings of the 12th international conference on Advanced communication technology
Latency-information theory: the mathematical-physical theory of communication-observation
Sarnoff'10 Proceedings of the 33rd IEEE conference on Sarnoff
Algebraic model for the behaviour of a D-flip-flops-based memory component
MAMECTIS'10 Proceedings of the 12th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Advances in Software Engineering - Special issue on software test automation
Information Sciences: an International Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An accurate circuit idea for pre-paid electricity for portable devices
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
Algebraic model for the CPU logic unit behaviour
Proceedings of the 15th WSEAS international conference on Computers
Linking anonymous transactions: the consistent view attack
PET'06 Proceedings of the 6th international conference on Privacy Enhancing Technologies
Controller synthesis by petri nets modeling
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
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From the Publisher:This is a modern revision of the classic digital design textbook. The book teaches the basic tools for the design of digital circuits in a clear, easily accessible manner. New to This Edition: Nine sections on Verilog Hardware Description Language (HDL) inserted in discrete sections, allowing the material to be covered or skipped as desired. The Verilog HDL presentation is at a suitable level for beginning students who are learning digital circuits for the first time. Reorganized material on combinational circuits is now covered in a single chapter. The emphasis in the sequential circuits chapters is now on design with D flip-flops instead of JK and SR flip-flops. The material on memory and programmable logic is now consolidated in one chapter. Chapter 8 consists mostly of new material and now covers digital design in the Register Transfer Level (RTL), preparing the reader for more advanced design projects and further Verilog HDL studies. A new section in Chapter 11 supplements the laboratory experiments with HDL experiments. These enable the reader to check the circuits designed in the laboratory by means of hardware components and/or by HDL simulation. Text accompanied by Verilog simulator softwareSynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in a design. All of the HDL examples in thebook can be found on the CD-ROM. A Companion Website includes resources for instructors and students such as transparency masters of all figures in the book, all HDL code examples from the book, a Verilog tutorial, tutorials on using the VeriLogger Pro software, and more. CONTENTS Binary Systems Boolean Algebra and Logic Gates Gate-Level Minimization Combinational Logic Synchronous Sequential Logic Registers and Counters Memory and Programmable Logic Register Transfer Level Asynchronous Sequential Logic Digital Integrated Circuits Laboratory Experiments Standard Graphic Symbols