Quantum computation and quantum information
Quantum computation and quantum information
Digital Design
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Approaching the Physical Limits of Computing
ISMVL '05 Proceedings of the 35th International Symposium on Multiple-Valued Logic
Introduction to reversible computing: motivation, progress, and challenges
Proceedings of the 2nd conference on Computing frontiers
Synthesis of reversible sequential elements
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Bi-Directional Synthesis of 4-Bit Reversible Circuits
The Computer Journal
Reversible computing and cellular automata—A survey
Theoretical Computer Science
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
Journal of Electronic Testing: Theory and Applications
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
Optimized reversible binary-coded decimal adders
Journal of Systems Architecture: the EUROMICRO Journal
An Introduction to Reversible Latches
The Computer Journal
Efficient approaches for designing reversible Binary Coded Decimal adders
Microelectronics Journal
Efficient Reversible Logic Design of BCD Subtractors
Transactions on Computational Science III
On figures of merit in reversible and quantum logic designs
Quantum Information Processing
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Power consumption in reversible logic addressed by a ramp voltage
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible cascades with minimal garbage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reversible circuits: recent accomplishments and future challenges for an emerging technology
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Mach-zehnder interferometer based design of all optical reversible binary adder
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Trading off circuit lines and gate costs in the synthesis of reversible logic
Integration, the VLSI Journal
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Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.