Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Reversible Logic Synthesis for Minimization of Full-Adder Circuit
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Synthesis of Full-Adder Circuit Using Reversible Logic
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Bi-Direction Synthesis for Reversible Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Design of a compact reversible binary coded decimal adder circuit
Journal of Systems Architecture: the EUROMICRO Journal
A Novel Approach to Design BCD Adder and Carry Skip BCD Adder
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Minimal energy dissipation in logic
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Toffoli network synthesis with templates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Comment on “Efficient approaches for designing reversible Binary Coded Decimal adders”
Microelectronics Journal
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An efficient approach for designing and minimizing reversible programmable logic arrays
Proceedings of the great lakes symposium on VLSI
On the compact designs of low power reversible decoders and sequential circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Design of efficient reversible logic-based binary and BCD adder circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low-power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well.