Exact sat-based toffoli network synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Six Synthesis Methods for Reversible Logic
Open Systems & Information Dynamics
Reversible circuit technology mapping from non-reversible specifications
Proceedings of the conference on Design, automation and test in Europe
Techniques for the synthesis of reversible Toffoli networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast exact Toffoli network synthesis of reversible logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reversible logic synthesis with Fredkin and Peres gates
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Pairwise decomposition of toffoli gates in a quantum circuit
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Efficient approaches for designing reversible Binary Coded Decimal adders
Microelectronics Journal
A novel Toffoli network synthesis algorithm for reversible logic
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An XQDD-Based Verification Method for Quantum Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Novel RM-Based Algorithm for Reversible Circuits
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
A Novel Transformation-Based Algorithm for Reversible Logic Synthesis
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
Reversible online BIST using bidirectional BILBO
Proceedings of the 7th ACM international conference on Computing frontiers
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
Reversible circuit synthesis using a cycle-based approach
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Rule-based optimization of reversible circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Optimization of reversible circuits using reconfigured templates
RC'11 Proceedings of the Third international conference on Reversible Computation
RevKit: an open source toolkit for the design of reversible circuits
RC'11 Proceedings of the Third international conference on Reversible Computation
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
Exploiting negative control lines in the optimization of reversible circuits
RC'13 Proceedings of the 5th international conference on Reversible Computation
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.03 |
Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the above synthesis approach. We present a basic method and, based on that, a bidirectional synthesis algorithm which produces a network of Toffoli gates realizing a given reversible specification. An asymptotically optimal modification of the basic synthesis algorithm employing generalized mEXOR gates is also presented. Transformations are then applied using template matching. The basis for a template is a network of gates that realizes the identity function. If a sequence of gates in the synthesized network matches a sequence comprised of more than half the gates in a template, then a transformation using the remaining gates in the template can be applied resulting in a reduction in the gate count for the synthesized network. All templates with up to six gates are described in this paper. Experimental results including an exhaustive examination of all 3-variable reversible functions and a collection of benchmark problems are presented. The paper concludes with suggestions for further research.