Exact sat-based toffoli network synthesis

Authors:
Daniel Große;Xiaobo Chen;Gerhard W. Dueck;Rolf Drechsler
Affiliations:
University of Bremen, Bremen, Germany;University of Bremen, Bremen, Germany;University of New Brunswick, Fredericton, Canada;University of Bremen, Bremen, Germany
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

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Abstract

Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoligates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean Satisfiability (SAT) instances. Such an instance is satisfiable if there exists a network representation with d gates. Thus, we can guarantee minimality. In addition to fully specified reversible functions, the algorithm can be applied to incompletely specified functions. For a set of benchmarks experimental results are given.