A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
Fault Testing for Reversible Circuits
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Multi-Output Galois Field Sum of Products Synthesis with New Quantum Cascades
ISMVL '03 Proceedings of the 33rd International Symposium on Multiple-Valued Logic
Exact sat-based toffoli network synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Synthesis of reversible sequential elements
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Heuristic methods to use don't cares in automated design of reversible and quantum logic circuits
Quantum Information Processing
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Controlled gates for multi-level quantum computation
Quantum Information Processing
Efficient circuits for exact-universal computationwith qudits
Quantum Information & Computation
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a synthesis method for combinational multiple-valued reversible logic (MVRL) circuits is proposed. This algorithm can use the don't care values in the synthesis process to obtain the optimal circuit with respect to quantum cost. The binary Fredkin gate is extended to the MVRL Fredkin gate, and its synthesis using 2x2 gates is proposed. Additionally, we have used the algorithm to design sequential MVRL circuits based on the state transition table. We propose three generalized designs for T, D, and JK flip flops (FF). The generalized r-valued T-FF is designed using 2r-3 controlled Cycle gates (r stands for radix). The r-valued D-FF is designed using the new version of the MVRL Fredkin gate. The ternary JK-FF, which performs nine distinct functions, is designed using only seven controlled Cycle gates. These FFs are the essential circuits to design MVRL state machines, and we synthesize the circuits with the minimal number of constant inputs and garbage outputs.