Fault Testing for Reversible Circuits

  • Authors:
  • Ketan N. Patel;John P. Hayes;Igor L. Markov

  • Affiliations:
  • -;-;-

  • Venue:
  • VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
  • Year:
  • 2003

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Abstract

Irreversible computation necessarily results in energy dissipationdue to information loss. While small in comparison to thepower consumption of today's VLSI circuits, if current trends continuethis will be a critical issue in the near future. Reversiblecircuits offer an alternative that, in principle, allows computationwith arbitrarily small energy dissipation. Furthermore, reversiblecircuits are essential components of quantum logic. We considerthe problem of testing these circuits, and in particular, generatingefficient test sets. The reversibility property significantly simplifiesthe problem, which is generally hard for the irreversible case.We discuss conditions for a test set to be complete, give a numberof practical constructions, and consider test sets for worst-casecircuits. In addition, we formulate the problem of finding minimaltest sets into an integer linear program (ILP) with binaryvariables. While this ILP method is infeasible for large circuits,we show that combining it with a circuit decomposition approachyields a practical alternative.