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IBM Journal of Research and Development
Transformation rules for designing CNOT-based quantum circuits
Proceedings of the 39th annual Design Automation Conference
Quantum computation and quantum information
Quantum computation and quantum information
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VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
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ATS '04 Proceedings of the 13th Asian Test Symposium
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ATS '04 Proceedings of the 13th Asian Test Symposium
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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A Family of Logical Fault Models for Reversible Circuits
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Optimum Test Set for Bridging Fault Detection in Reversible Circuits
ATS '07 Proceedings of the 16th Asian Test Symposium
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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VLSID '08 Proceedings of the 21st International Conference on VLSI Design
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IBM Journal of Research and Development
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IBM Journal of Research and Development
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ACM Journal on Emerging Technologies in Computing Systems (JETC)
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COCOON'10 Proceedings of the 16th annual international conference on Computing and combinatorics
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Journal of Electronic Testing: Theory and Applications
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault testing for reversible circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Derivation of test set for detecting multiple missing-gate faults in reversible circuits
Computers and Electrical Engineering
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Computers and Electrical Engineering
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This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an (nxn) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate, yields an easily testable design, which admits a universal test set (UTS) of size (n+1) that detects all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) in the circuit. Furthermore, storage of only one vector (seed) of the UTS is required; the rest can be generated by n successive cyclic bit-shifts from the seed. For fault location under the SMGF model, a technique for identifying the faulty gate is also presented that needs application of a single test vector, provided the circuit is augmented with some additional observable outputs.