Optimum Test Set for Bridging Fault Detection in Reversible Circuits

  • Authors:
  • Hafizur Rahaman;Dipak K. Kole Dipak K. Kole;Debesh K. Das;Bhargab B. Bhattacharya

  • Affiliations:
  • University, Howrah 711 103, India;University, Howrah 711 103, India;University, Howrah 711 103, India;ACM Unit, Indian Statistical Institute, Kolkata

  • Venue:
  • ATS '07 Proceedings of the 16th Asian Test Symposium
  • Year:
  • 2007

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Abstract

Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n · n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd2 log2n). A test set of cardinality O(d log2n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.