A Novel Approach for On-line Testable Reversible Logic Circuit Design

Authors:
D. P. Vasudevan;P. K. Lala;J. P. Parkerson
Affiliations:
University of Arkansas;University of Arkansas;University of Arkansas
Venue:
ATS '04 Proceedings of the 13th Asian Test Symposium
Year:
2004

Citing 0
Cited 2

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Abstract

Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.