Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
Journal of Electronic Testing: Theory and Applications
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates
Journal of Electronic Testing: Theory and Applications
On the fault testing for reversible circuits
ISAAC'07 Proceedings of the 18th international conference on Algorithms and computation
Universal test sets for reversible circuits
COCOON'10 Proceedings of the 16th annual international conference on Computing and combinatorics
Fault diagnosis in reversible circuits under missing-gate fault model
Computers and Electrical Engineering
Derivation of test set for detecting multiple missing-gate faults in reversible circuits
Computers and Electrical Engineering
Online Testable Approaches in Reversible Logic
Journal of Electronic Testing: Theory and Applications
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Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets TUTS such that each C(n) has a unique test set T(n) in TUTS that detects all F-type faults in every member of C(n). We show that if k 驴 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n虏 + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cellýs state table.