On the fault testing for reversible circuits

Authors:
Satoshi Tayu;Shigeru Ito;Shuichi Ueno
Affiliations:
Department of Communications and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan;Department of Communications and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan;Department of Communications and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan
Venue:
ISAAC'07 Proceedings of the 18th international conference on Algorithms and computation
Year:
2007

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Abstract

This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit. We also show non-trivial lower bounds for the size of a minimum complete test set.