Quantum computation and quantum information
Quantum computation and quantum information
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
Testing for Missing-Gate Faults in Reversible Circuits
ATS '04 Proceedings of the 13th Asian Test Symposium
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Introduction to reversible computing: motivation, progress, and challenges
Proceedings of the 2nd conference on Computing frontiers
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic
Proceedings of the 2nd conference on Computing frontiers
A Family of Logical Fault Models for Reversible Circuits
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Synthesis of reversible logic for nanoelectronic circuits: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectronic Circuits
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
Minimization of CTS of k-CNOT Circuits for SSF and MSF Model
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
On figures of merit in reversible and quantum logic designs
Quantum Information Processing
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
ESOP-Based Toffoli Network Generation with Transformations
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Rule-based optimization of reversible circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Online fault testing of reversible logic using dual rail coding
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
ISMVL '11 Proceedings of the 2011 41st IEEE International Symposium on Multiple-Valued Logic
Online Fault Detection in Reversible Logic
DFT '11 Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault testing for reversible circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum Circuit Simplification and Level Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
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We present an overview and analysis of existing work in the design of online testable reversible logic circuits, as well as propose new approaches for the design of such circuits. We explain how previously proposed approaches are unnecessarily high in overhead and in many cases do not provide adequate fault coverage. Proofs of the correctness of our approaches are provided, and discussions of the advantages and disadvantages of each design approach are given. Experimental results comparing our approaches to existing work are presented as well. Both approaches that we propose have better fault coverage and significantly lower overheads than previous approaches.