Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
AC-1: a clock-powered microprocessor
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A three-port nRERL register file for ultra-low-energy applications
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
An 8×8 nRERL serial multiplier for ultra-low-power aplications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
True single-phase adiabatic circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Complexity reduction in an nRERL microprocessor
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Online Testable Approaches in Reversible Logic
Journal of Electronic Testing: Theory and Applications
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We describe a simple 8-bit adiabatic microprocessor implemented with nMOS reversible energy recovery logic (nRERL) [1]. The implemented adiabatic microprocessor supports only a subset of the DLX instruction set architecture [15] in order to be fitted into a limited silicon area, and is integrated with an energy-efficient 6-phase clocked power generator (CPG). Phase scheduling was employed to reduce the number of the buffers required in the adiabatic microprocessor. Furthermore, reversibility breaking with self-energy recovery circuits (SERCs) was also employed to reduce energy consumption as well as circuit complexity by. The 8-bit microprocessor core and its on-chip 6-phase CPG were implemented in 0.18-mm CMOS technology. The former and the latter occupied 2.62 x 2.03 mm2 and 1.0 x 0.6 mm2, respectively. From the measurements, we have found that its minimum power consumption is 7.5μW at Vdd =1.8V and f=880kHz