A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy Efficient Adiabatic Multiplier-Accumulator Design
Journal of VLSI Signal Processing Systems
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
Ultralow-power adiabatic circuit semi-custom design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic
Proceedings of the 2nd conference on Computing frontiers
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A CMOS compatible charge recovery logic family for low supply voltages
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Dynamic logic families that rely on energy recovery to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme. We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 /spl mu/m standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our andbit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts.