The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Design and Evaluation of Adiabatic Arithmetic Units
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Single-phase source-coupled adiabatic logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
True single-phase adiabatic circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
A secure and low-energy logic style using charge recovery approach
Proceedings of the 13th international symposium on Low power electronics and design
Low-power interface circuits between adiabatic and standard CMOS circuits
Analog Integrated Circuits and Signal Processing
Energy efficient interface circuits between adiabatic and standard CMOS logic at 90 nm technology
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Adiabatic and standard CMOS interfaces at 90 nm technology
WSEAS Transactions on Circuits and Systems
Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles
Integration, the VLSI Journal
Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-µm CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3 ÷ 6) even when the losses in power-clock generation are considered.