2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Ultralow-power adiabatic circuit semi-custom design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
IEICE - Transactions on Information and Systems
An energy-aware active smart card
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 μm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.