2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Basic methods of cryptography
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Low-Power CAM Design for LZ Data Compression
IEEE Transactions on Computers
A Single Clocked Adiabatic Static Logic—A Proposal for Digital Low Power Applications
Journal of VLSI Signal Processing Systems
Smart Card Handbook
Wake on wireless: an event driven energy saving strategy for battery operated devices
Proceedings of the 8th annual international conference on Mobile computing and networking
A Forward-Secure Digital Signature Scheme
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Smart Cards - Requirements, Properties, and Applications
State of the Art in Applied Cryptography, Course on Computer Security and Industrial Cryptography - Revised Lectures
Experience with a low power wireless mobile computing platform
Proceedings of the 2004 international symposium on Low power electronics and design
Forward-security in private-key cryptography
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Low-power interface circuits between adiabatic and standard CMOS circuits
Analog Integrated Circuits and Signal Processing
Energy efficient interface circuits between adiabatic and standard CMOS logic at 90 nm technology
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Adiabatic and standard CMOS interfaces at 90 nm technology
WSEAS Transactions on Circuits and Systems
Security'12 Proceedings of the 21st USENIX conference on Security symposium
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Despite recent advances in smart card technology, most modern smart cards continue to rely on card readers for power and clocking, creating a potential security gap. In this paper, we present an energy-aware smart card architecture that operates using an embedded battery and crystal. This low-power VLSI system is continually active and provides enhanced security through periodic internal update when the card is detached from a reader. Our architecture achieves reduced power consumption by deactivating the majority of its circuitry, including an embedded microcontroller, for the vast majority of the card's lifetime. A proof-of-concept prototype implementation of the architecture has been developed including register-transfer-level and gate-level designs which have been synthesized to silicon. To permit extended operation for up to 18 months, critical design logic has been implemented using ultralow-power (adiabatic) circuit techniques.