Microelectronics, 2nd ed.
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Two phase clocked adiabatic static CMOS logic
SOC'09 Proceedings of the 11th international conference on System-on-chip
An energy-aware active smart card
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical ‘1’ and ‘0’ states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.