Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
AC-1: a clock-powered microprocessor
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
True single-phase energy-recovering logic for low-power, high-speed VLSI
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Single-phase source-coupled adiabatic logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
True single-phase adiabatic circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
Asymptotically zero energy computing using split-level charge recovery logic
Asymptotically zero energy computing using split-level charge recovery logic
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
Charge-Recovery Computing on Silicon
IEEE Transactions on Computers
Fast, efficient, recovering, and irreversible
Proceedings of the 2nd conference on Computing frontiers
Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-µm standard n-well CMOS process, the chip has an active area of 0.47 mm2. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.