Locally clocked pipelines and dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8 bit multiplier design that operates at 715 MHz in a 1.0mm MOSIS process, which exceeds the highest multiplier frequency previously published.