Communications of the ACM
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Implementation of micropipelines in enable/disable CMOS differential logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
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Micropipelines and most of its variants use a delay-insensitive controller to moderate a pipeline. In search of improved performance, we depart from the delay-insensitive model in favor of a bounded-delay model for the controller. In particular, we demonstrate how a general delay-insensitive controller for level-sensitive pipelines can be improved by assuming a bounded-delay model and taking advantage of delay information to make the controller faster and more efficient. The new control scheme is referred to as locally clocked (LC) control. A highly pipelined logic technique called LC dynamic logic is presented that combines the bounded-delay controller with a latching dynamic logic gate design. Simulations comparing LC control with its delay-insensitive counterpart are presented. Also, an 8 x 8 bit multiplier with a maximum frequency of 715 MHz for a 1 &mgr;m CMOS process that uses LC dynamic logic is presented.