Mixed-swing quadrail for low power dual-rail domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Monotonic static CMOS and dual-VT technology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Implication graph based domino logic synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Locally clocked pipelines and dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pipelined clock-delayed domino carry-lookahead adder
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Output Prediction Logic: A High-Performance CMOS Design Technique
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Clock delayed domino logic with efficient variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed low-power multiplexer-based selector for priority policy
Computers and Electrical Engineering
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An innovative dynamic logic family, clock-delayed (CD) domino, was developed to provide gates with either inverting or non-inverting outputs, and the high speed and layout compactness of dynamic logic. The characteristics of CD domino are demonstrated in two carry lookahead adder designs and three MCNC combinational logic benchmark circuits. The CD domino designs are compared to designs using static CMOS and standard domino logic. A circuit design tool was developed to automate the design of CD domino circuits. Simulations show a 32-bit CD domino adder comprised of four 8-bit full adders to be 30% faster than a 32-bit standard domino adder, and a 32-bit CD domino adder comprised of a single 32-bit full adder to be 45% faster. In the combinational logic benchmark circuits, complex inverting and non-inverting gates were used to implement C1355, C3540, and b9. The CD domino circuits were 22%, 43% and 34% faster than their static CMOS counterparts of C1355, C3540 and b9, respectively.