Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel instruction stream buffer for VLIW architectures
Computers and Electrical Engineering
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block
ISED '11 Proceedings of the 2011 International Symposium on Electronic System Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The nature of priority policy causes inefficient throughput in synchronous clock systems because of an unbalanced propagation path. To improve speed, the proposed priority scheme improves extremely unbalanced delays between the highest and lowest weight by integrating the multiplexer-based date selector with the priority encoder. Balanced propagation paths are analyzed based on the gate-level evaluation and demonstrated by post-layout simulation. In terms of scalability, this design is suitable for extending width and has a latency of only O(logm) for m requests. The proposed design also improves the critical path by using delayed-precharge technology for dynamic logic and transmission gate at transistor level. The simulation results show that, for 8-128 requests cases, this approach achieves balanced propagation paths from fastest to lowest path. The proposed design achieves a 4.5 speedup and a 57.2% decrease in power dissipation.