Implication graph based domino logic synthesis

Authors:
Ki-Wook Kim;C. L. Liu;Sung-Mo Kang
Affiliations:
Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL;Department of Computer Science, National Tsing Hua University, Hsin-Chu, Taiwan 30043;Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

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Abstract

In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on implication graph can reduce transistor counts by 25% and power delay product by 25% on average.