DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Introduction to algorithms
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Logic optimization by output phase assignment in dynamic logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
On accelerating pattern matching for technology mapping
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Domino logic synthesis using complex static gates
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of the ACM (JACM)
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
Implication graph based domino logic synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Design Automation for Timing-Driven Layout Synthesis
Design Automation for Timing-Driven Layout Synthesis
Design Issues in Mixed Static-Domino Circuit Implementations
ICCD '98 Proceedings of the International Conference on Computer Design
Computing the area versus delay trade-off curves in technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C5M-a control-logic layout synthesis system for high-performance microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven partitioning and timing optimization of mixed static-domino implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low power synthesis of dynamic logic circuits using fine-grained clock gating
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We present an efficient algorithm for technology mapping of domino logic to a parameterized library. The algorithm is optimal for mapping trees consisting of two-input AND/OR nodes, and has a computation time that is polynomial in terms of constraint size. The mapping method is then extended to DAG covering that permits the implicit duplication of logic nodes. Our synthesis procedure maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dual-monotonic gates in the case of XOR/XNOR logic. The mapping procedure solves the output phase assignment problem as a preprocessing step. Based on a key observation that the output phase assignment could reduce the implementation cost due to the possible large cost difference between two polarities, a 0--1 integer linear programming formulation was designed to minimize the implementation cost. Our experimental results show the effectiveness of the proposed techniques.