Design Automation for Timing-Driven Layout Synthesis

Clustered voltage scaling technique for low-power design

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Technology mapping algorithms for domino logic

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Implementation and extensibility of an analytic placer

Proceedings of the 2004 international symposium on Physical design

Supply Voltage Degradation Aware Analytical Placement

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Stochastic power/ground supply voltage prediction and optimization via analytical placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

BDD decomposition for delay oriented pass transistor logic synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems