Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An Adaptive Nonlinear Least-Squares Algorithm
ACM Transactions on Mathematical Software (TOMS)
Design Automation for Timing-Driven Layout Synthesis
Design Automation for Timing-Driven Layout Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Practical methodology of post-layout gate sizing for 15% more power saving
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Linear programming for sizing, Vth and Vdd assignment
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A novel approach for variation aware power minimization during gate sizing
Proceedings of the 2006 international symposium on Low power electronics and design
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for sizing sequential circuits for industrial library based designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A class of problems for which cyclic relaxation converges linearly
Computational Optimization and Applications
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
A quick method for energy optimized gate sizing of digital circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
Speed indicators for circuit optimization
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Fast and efficient lagrangian relaxation-based discrete gate sizing
Proceedings of the Conference on Design, Automation and Test in Europe
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-processing step that provides an effective set of initial Lagrange multipliers. Compared to the previous Lagrangian-based approach, Forge is considerably faster and does not have the inefficiencies due to difficult-to-determine initial conditions and constant factors. We compared the two algorithms on 30 benchmark designs, on a Sun UltraSparc-60 workstation. On average Forge is 200 times faster than the previously published algorithm. We then improved Forge by incorporating a slew-rate-based convex delay model, which handles distinct rise and fall gate delays. We show that Forge is 15 times faster, on average, than the AMPS transistor-sizing tool from Synopsys, while achieving the same delay targets and using similar total transistor area.