Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Post-layout transistor sizing for power reduction in cell-based design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
This paper presents a practical methodology of post-layout gate sizing for power reduction. Wire capacitance presumed in logic synthesis typically contains excessive margin for better timing closure in layout design. Power waste due to this can be reduced by post-layout gate sizing based on information obtained by backannotation. In this paper, we discuss a theory of optimal gate sizing in a signal path with surplus timing. We also, propose a practical design methodology where standard cells are reselected from a cell library by the theory, replaced by engineering change order, and timing constraints are verified by a static timing analyzer. We have applied the methodology to a 700k-gate commercial application processor for 3G cellular phones. Even though the original design was optimized for 133MHz, 170mW operation in a 0.18μm CMOS technology, power dissipation was further squeezed by 15% in combinational logic without compromising the performance.