Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A power optimization method considering glitch reduction by gate sizing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power reduction by simultaneous voltage scaling and gate sizing
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
An Adaptive Interconnect-Length Driven Placer
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Practical methodology of post-layout gate sizing for 15% more power saving
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Probabilistic Delay Budgeting for Soft Realtime Applications
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Probabilistic delay budget assignment for synthesis of soft real-time applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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