Power reduction by simultaneous voltage scaling and gate sizing

  • Authors:
  • Chunhong Chen;Majid Sarrafzadeh

  • Affiliations:
  • Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL;Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL

  • Venue:
  • ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
  • Year:
  • 2000

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Abstract