A symbolic method to reduce power consumption of circuits containing false paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power reduction by simultaneous voltage scaling and gate sizing
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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In this paper we present a new library-oriented cell selection approach to minimize power consumption of combinational circuits. Our unified Mixed Integer Linear-Programming (MILP) formulation selects library cells with different gate sizes, supply voltages and threshold voltages simultaneously during technology mapping. Experimental results on bench-marks mapped to an industrial library show that our technique achieves 19% more power saving in less CPU time comparing with other approaches.