Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits

Authors:
Pankaj Pant;Vivek K. De;Abhijit Chatterjee
Affiliations:
Georgia Institute of Technology, Atlanta;Intel Corp., Hillsboro, OR;Georgia Institute of Technology, Atlanta
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1998

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Abstract

This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.