Circuit techniques for low-power CMOS GSI
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Power Aware Design Methodologies
Power Aware Design Methodologies
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI
Proceedings of the 2003 international symposium on Low power electronics and design
Hi-index | 0.00 |
This paper describes an efficient hierarchical design and optimization approach for ultra-low power CMOS logic circuits. We introduce the Hierarchical Activity-Aware Time Slack Distribution (HA2TSD) algorithm, which distributes the surplus time slack into the most power-hungry modules hierarchically. HA2TSD ensures that the total slack budget is maximal and the total power is near-minimal. Based on these time slacks, we have optimized technology parameters (supply voltage, threshold voltage, and device width) through a gate-level power optimizer and have tested the algorithm on a set of benchmark example circuits and building blocks of a synthesizable ARM core. The experimental results show that our strategy delivers over an order of magnitude savings in total (static and dynamic) power and reduces the optimization run-time significantly.