Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Optimization of VDD and VTH for low-power and high speed applications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Low-power circuits using dynamic threshold devices
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Variability and energy awareness: a microarchitecture-level perspective
Proceedings of the 42nd annual Design Automation Conference
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Peak temperature control and leakage reduction during binding in high level synthesis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Energy-delay minimization in nanoscale domino logic
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic power management under uncertain information
Proceedings of the conference on Design, automation and test in Europe
Resilient dynamic power management under uncertainty
Proceedings of the conference on Design, automation and test in Europe
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Uncertainty-aware dynamic power management in partially observable domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (Vdd) and threshold (Vth) voltages. We present for the first time, the implications of an electrothermally aware EDP optimization on circuit operation in leakage dominant nanometer scale CMOS technologies. It is demonstrated that electrothermal EDP (EEDP) optimization restricts the operation of the circuit to a certain region in the Vdd-Vth plane. Also, the significance of EEDP optimization has been shown to increase with increase in leakage power and/or process variations.