Energy-delay minimization in nanoscale domino logic

Authors:
Bo Fu;Qiaoyan Yu;Paul Ampadu
Affiliations:
University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY
Venue:
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Year:
2006

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Abstract

Energy-delay product (EDP) minimization in nanoscale domino logic circuits by supply voltage selection and device sizing is presented. It is shown that the dependence of leakage current on transistor width introduces an additional factor in sizing for leakage dominant circuit blocks. A model is presented for EDP-optimal sizing of the evaluation tree of domino AND-type gates, and the effects of sizing the static output inverter and keeper on EDP are discussed. The model is applied to an 8x8 carry-save multiplier, which achieves 10% reduction in EDP at low frequencies compared to minimum width sizing.