Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
Proceedings of the 2004 international symposium on Low power electronics and design
Energy-delay minimization in nanoscale domino logic
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A design methodology for temperature variation insensitive low power circuits
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Leakage-aware intraprogram voltage scaling for embedded processors
Proceedings of the 43rd annual Design Automation Conference
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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We provide a unified first-order analysis of optimal voltage scaling and transistor sizing for minimum energy-delay product. Based on such calculations we show that a circuit design style with separate logic and buffer improves the energy-delay product by almost an order of magnitude in the presence of interconnect parasitics. We also show that the power supply voltage for minimum energy-delay product is slightly larger than two times the optimal threshold voltage Vth and the ratio of AC power and DC power for minimum energy-delay product is approximately two thirds of the optimal ratio of Vth and the thermal voltage VT.