Design of analog-digital VLSI circuits for telecommunications and signal processing
A minimum total power methodology for projecting limits on CMOS GSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Optimization of VDD and VTH for low-power and high speed applications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Ultra-low power DLMS adaptive filter for hearing aid applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal Voltages and Sizing for Low Power
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes
IEEE Transactions on Computers
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Robust Design of High Fan-In/Out Subthreshold Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Analysis and optimization of sleep modes in subthreshold circuit design
Proceedings of the 44th annual Design Automation Conference
Nanometer device scaling in subthreshold circuits
Proceedings of the 44th annual Design Automation Conference
Energy efficient near-threshold chip multi-processing
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A 0.4-V UWB baseband processor
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Vt balancing and device sizing towards high yield of sub-threshold static logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Statistical noise margin estimation for sub-threshold combinational circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Microelectronics Journal
Reconfigurable energy efficient near threshold cache architectures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays
Microelectronics Journal
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Dynamic voltage-frequency scaling in body area sensor networks using COTS components
BodyNets '09 Proceedings of the Fourth International Conference on Body Area Networks
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System energy minimization via joint optimization of the DC-DC converter and the core
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design
Proceedings of the 48th Design Automation Conference
Variability-speed-consumption trade-off in near threshold operation
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Detecting stability faults in sub-threshold SRAMs
Proceedings of the International Conference on Computer-Aided Design
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits
Proceedings of the 49th Annual Design Automation Conference
A fine-grained many VT design methodology for ultra low voltage operations
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Optimization for real-time systems with non-convex power versus speed models
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits
Journal of Signal Processing Systems
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Subthreshold operation is emerging as an energy-saving approach to many new applications. This paper examines energy minimization for circuits operating in the subthreshold region. We show the dependence of the optimum V DD for a given technology on design characteristics and operating conditions. Solving equations for total energy provides an analytical solution for the optimum V DD and V T to minimize energy for a given frequency in subthreshold operation. SPICE simulations of a 200K transistor FIR filter confirm the analytical solution and the dependence of the minimum energy operating point on important parameters.