Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Power-Delay Metrics Revisited for 90nm CMOS Technology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes
IEEE Transactions on Computers
Robust Design of High Fan-In/Out Subthreshold Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Analyzing and modeling process balance for sub-threshold circuit design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Vt balancing and device sizing towards high yield of sub-threshold static logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variability of flip-flop timing at sub-threshold voltages
Proceedings of the 13th international symposium on Low power electronics and design
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Microelectronics Journal
Subthreshold FIR Filter Architecture for Ultra Low Power Applications
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An energy-efficient subthreshold level converter in 130-nm CMOS
IEEE Transactions on Circuits and Systems II: Express Briefs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Timing modeling for digital sub-threshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Variation resilient adaptive controller for subthreshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Body bias generator for leakage power reduction of low-voltage digital logic circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Optimization for real-time systems with non-convex power versus speed models
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Dynamic supply and threshold voltage scaling for CMOS digital circuits using in-situ power monitor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power dissipation. Many applications including medical and wireless applications, require ultra low power dissipation with low-to-moderate performance (10kHz-100MHz). In this work, using BSIM3 models, the performance and energy dissipation of 0.18-mm CMOS circuits for the range of V_dd =0.1-0.6V and V th =0-0.6V, are analyzed to show that subthreshold CMOS circuits can be used in low performance applications. A simple characterization circuit is introduced which can be used to evaluate the performance and energy dissipation for a given process under varying activity. These results are useful in circuit design by giving insight into optimal voltage supply and threshold voltage operation for a given application specification. Characterization results show that operation at the optimal V dd -V th voltage levels can lead to an order of magnitude energy savings. Also additional analysis into V th and temperature variations is included.