Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Statistical noise margin estimation for sub-threshold combinational circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A fine-grained many VT design methodology for ultra low voltage operations
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Operating digital circuits in the sub-threshold region is potentially a solution for ultra low-power applications. However, simply reducing supply voltage well below threshold voltage causes functional yield degradation. In this paper, we show that imbalanced VT of pMOS and nMOS transistors and VT mismatch of paired transistors are especially detrimental to sub-threshold functional yield. We propose a variability-driven digital gate design approach which includes balancing process-corner VT shifts of nMOS/pMOS transistors with a low-overhead bulk-bias circuitry and a gate-sizing approach that yields close to minimum size transistor dimensions. Results of Monte-Carlo simulations of a ring oscillator with 31 stages show that our solution can help to achieve a mean frequency speedup of 51.91% and energy/cycle saving of 19.67% on average.