Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Vt balancing and device sizing towards high yield of sub-threshold static logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Utilizing reverse short-channel effect for optimal subthreshold circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-edge flip-flops for improved timing yield: design and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library
Proceedings of the 48th Design Automation Conference
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In this paper, we propose a fine-grained many VT design methodology for ultra low voltage (ULV) operations of CMOS VLSI circuits. The fine-grained many VT transistors can be developed through only layout-level technique (e.g. inverse narrow width effects) in a multi-VT technology without any process modifications. Through SPICE simulations, we confirm that the proposed design methodology can improve performance, energy efficiency and variability of ULV circuits in three important domains, i.e. driving a fixed capacitive load, reducing active leakage energy consumption in non-critical paths, and lengthening short delay paths without energy overhead to aid error detection and correction techniques.