Maximizing performance by retiming and clock skew scheduling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops
Proceedings of the 13th international symposium on Low power electronics and design
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Using soft-edge flip-flops to compensate NBTI-induced delay degradation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
MicroFix: Using timing interpolation and delay sensors for power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fine-grained many VT design methodology for ultra low voltage operations
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Parameter variations cause high yield losses due to their large impact on circuit delay. In this paper, we propose the use of so-called soft-edge flip-flops as an effective way to mitigate these yield losses. Soft-edge flip-flops have a small window of transparency (ranging from 0.25-3 FO4) instead of a hard edge, allowing limited cycle stealing on critical paths, and thus compensating for delay variations. By enabling time borrowing, soft-edge flip-flops allow random delay variations to average out across multiple logic stages. In addition, they address small amounts of delay imbalance between logic stages, further maximizing the frequency of operation. We develop a library of soft-edge flip-flops with varying amounts of softness. We show that the power and area overhead of soft-edge flip-flops grows directly with the amount of softness. We then propose a statistically aware flip-flop assignment algorithm that maximizes the gain in timing yield while minimizing the incurred power overhead. Experimental results on a wide range of benchmark circuits show that the proposed approach improves the mean delay by 1.9--22.3% while simultaneously reducing the standard deviation of delay by 1.9--24.1% while increasing power by a small amount (0.3--2.8%).