IEEE Transactions on Computers
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Maximizing performance by retiming and clock skew scheduling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clustering based fast clock scheduling for light clock-tree
Proceedings of the conference on Design, automation and test in Europe
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A self-adjusting clock tree architecture to cope with temperature variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Unified adaptivity optimization of clock and logic signals
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Soft-edge flip-flops for improved timing yield: design and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Useful-skew clock optimization for multi-power mode designs
Proceedings of the International Conference on Computer-Aided Design
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
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This paper exploits useful skew to improve system performance and robustness. We formulate a robust integer linear programming problem considering the interactions between data and clock paths on a microprocessor chip to improve clock frequency. The timing slack is optimized for each path to determine a clock schedule. The percentage of timing violations, obtained from a 1000 point Monte Carlo simulation, is higlighted as yield predictions and conveys the robustness of the clock schedule. The results show performance improvement of up to 9.747% with 20% yield and up to 6.682% with 100% yield. The novelty of the proposed method is its ability to tradeoff between performance improvement in frequency and robustness, via a single variable in the formulation.