Systolic Evaluation of Polynomial Expressions
IEEE Transactions on Computers
IEEE Transactions on Computers
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
A Design of Reed-Solomon Decoder with Systolic-Array Structure
IEEE Transactions on Computers
A polynomial combinatorial algorithm for generalized minimum cost flow
STOC '99 Proceedings of the thirty-first annual ACM symposium on Theory of computing
Reducing pipeline energy demands with local DVS and dynamic retiming
Proceedings of the 2004 international symposium on Low power electronics and design
WITHIN DIE THERMAL GRADIENT IMPACT ON CLOCK-SKEW: ANEW TYPE OF DELAY-FAULT MECHANISM
ITC '04 Proceedings of the International Test Conference on International Test Conference
A fast digit-serial systolic multiplier for finite field GF(2m)
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated design of self-adjusting pipelines
Proceedings of the 45th annual Design Automation Conference
Inversed temperature dependence aware clock skew scheduling for sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel binary linear programming for high performance clock mesh synthesis
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Ensuring resilience against environmental variations is becoming one of the great challenges of chip design. In this paper, we propose a self adjusting clock tree architecture, SACTA, to improve chip performance and reliability in the presence of on-chip temperature variations. SACTA performs temperature dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. We present an automatic temperature adjustable skew buffer design, which enables the adaptive feature of SACTA. Furthermore, we propose an efficient and general optimization framework to determine the configuration of these special delay elements. Experimental results show that a pipeline supported by SACTA is able to prevent thermal induced timing violations within a significantly larger range of operating temperatures (enhancing the violation-free range by as much as 45°C).