A fast digit-serial systolic multiplier for finite field GF(2m)

Authors:
Chang Hoon Kim;Soonhak Kwon;Chun Pyo Hong
Affiliations:
Daegu University, Jinryang, Kyungsan, Korea;Sungkyunkwan University, Suwon, Korea;Daegu University, Jinryang, Kyungsan, Korea
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

This paper presents a new digit-serial systolic multiplier over GF(2m) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every [m/D] + 2 clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.